1. Field of the Invention
The present invention relates to a plasma display panel (PDP) driving circuit. More specifically, the present invention relates to a driving circuit for preventing waveform distortion caused by impedance provided on a main discharge path.
2. Description of the Related Art
Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and plasma displays have been actively developed. The plasma displays panels (PDPs) from among the flat panel devices may have better luminance and light emission efficiency compared to the other types of flat panel devices, and also may have wider view angles. Therefore, the plasma displays may be suitable substitutes for conventional cathode ray tubes (CRTs) in large displays of greater than 40 inches.
A PDP generally is a flat display that uses plasma generated via a gas discharge process to display characters or images, and tens to millions of pixels are provided thereon in a matrix format, depending on its size. The two general kinds of PDPs are AC PDPs and DC PDPs, based on their respective driving voltage waveforms.
Because DC plasma displays have electrodes exposed in the discharge space, they allow electric current to flow in the discharge space while voltage is supplied. Therefore they problematically require resistors for current restriction. On the other hand, because AC plasma displays have electrodes covered by a dielectric layer, capacitances are naturally formed to restrict the current. Accordingly, the electrodes are protected from ion shocks during discharge. Thus, they have a longer lifespan than DC plasma displays.
FIG. 1 shows a perspective view of an AC PDP. As shown, a scan electrode 4 and a sustain electrode 5, disposed over a dielectric layer 2 and a protection film 3, may be provided in parallel and may form a pair with each other under a first glass substrate 1. A plurality of address electrodes 8 covered with an insulation layer 7 may be installed on a second glass substrate 6. Barrier ribs 9 may be formed in parallel with the address electrodes 8, on the insulation layer 7 between the address electrodes 8. Phosphor 10 may be formed on the surface of the insulation layer 7 between the barrier ribs 9. The first and second glass substrates 1 and 6 having a discharge space 11 between them may be provided facing each other so that the scan electrode 4 and the sustain electrode 5 may respectively cross the address electrode 8. The address electrode 8 and a discharge space 11 formed at a crossing part of the scan electrode 4 and the sustain electrode 5 may form a discharge cell 12.
FIG. 2 shows a PDP electrode arrangement diagram. As shown, the PDP electrode has an m×n matrix configuration, and in detail, it has address electrodes A1 to Am in the column direction, and scan electrodes Y1 to Yn and sustain electrodes X1 to Xn in the row direction, alternately. For ease of identification, the scan electrodes will be noted as “Y electrodes” and the sustain electrodes as “X electrodes.” The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG. 1.
FIG. 3 shows a PDP. As shown, the PDP comprises a plasma panel 10, an address driver 20, a scan/sustain driver 30, and a controller 40.
The plasma panel 10 comprises a plurality of address electrodes A1 to Am arranged in the column direction, and a plurality of scan electrodes Y1 to Yn and sustain electrodes X1 to Xn alternately arranged in the row direction.
The address driver 20 receives an address driving control signal from the controller 40, and applies display data signals for selecting discharge cells to be displayed to the respective address electrodes, and it comprises a power recovery circuit for recovering reactive power and reusing the same.
The scan/sustain driver 30 receives a sustain discharge signal from the controller 40, and alternately inputs sustain pulse voltages to the scan and sustain electrodes to thus perform a sustain discharge on the selected discharge cells.
The controller 40 receives external video signals, generates an address driving control signal and a sustain discharge signal, and respectively applies them to the address driver 20 and the scan/sustain driver 30.
FIG. 4 shows a conventional PDP driving circuit.
In general, the AC PDP is driven by a sustain period, an erase period, a reset period, and an address period, and the same is driven by using various waveforms.
The scan driving circuit comprises a power recovery circuit proposed by Weber disclosed in U.S. Pat. Nos. 4,866,349 and 5,081,400, a first ramp pulse supply 31, a second ramp pulse supply 32, and a scan voltage supply 33.
A conventional sustain discharge operation and a power recovery operation will be described.
A switch S4 is turned on before a switch S1 is turned on, and a voltage at a panel C2 is maintained at 0V. When the switch S1 is turned on, an LC resonance circuit is formed in the order of a capacitor C1 and the switch S1, and in the order of a diode D1, an inductor L1, and the panel C2, and the voltage at the panel C2 is increased to a voltage of Vs.
When the switch S1 is turned off and a switch S3 is turned on, zero voltage switching is performed and the voltage at the panel C2 is maintained at the voltage of +Vs because the voltage at the switch S3 is 0V.
When the switch S3 is turned off and a switch S2 is turned on, an LC resonance circuit is formed in the order of the panel C2, the inductor L1, a diode D2, the switch S2, and the capacitor C1, and the voltage at the panel C2 is reduced.
When the switch S2 is turned off and a switch S4 is turned on, zero voltage switching is performed and the voltage at the panel C2 is maintained at 0V because the voltage at the switch S4 is 0V.
The sustain discharge pulses are combined with the waveforms applied by the first ramp pulse supply 31, the second ramp pulse supply 32, and the scan voltage supply 33 to form various driving waveforms. In this instance, switches Ypp and Ynp on the main discharge path A are switched to supply various driving waveforms to the panel. The switches Ypp and Ynp need double path switches because an erase operation or a scan operation can be performed in a negative bias level.
However, the switches Ypp and Ynp formed on the main discharge path are causes to increase pattern impedance. That is, the pattern impedance formed on the main discharge path A formed between the electrode and the sustain discharge circuit distorts the waveforms and influences margins of the sustain voltage because of an overshot voltage.
FIGS. 5a and 5b show graphs for measuring influences of the pattern impedance of the main discharge path.
In consideration of the pattern impedance provided on the main discharge path as an inductance component, FIG. 5a shows a measured sustain discharge waveform without pattern impedance, and FIG. 5b shows a measured sustain discharge waveform with the pattern impedance of 0.01 μH.
As known from FIG. 5b, the time for the sustain discharge waveform to reach the steady state is delayed because of the pattern impedance formed on the main discharge path, and a large overshoot is generated. Therefore, the pattern impedance decreases the margin of the sustain discharge voltage and damages stability of the waveforms.